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mdt10p74(ba) this specification are subject to be change d without notice. any latest information please preview http;//www.mdtic.com.tw p. 1 2008/6 ver. 1.6 q1. general description this eprom-based 8-bit micro-c ontroller uses a fully static cmos technology process to achieve higher speed and smaller size with the low power consumption and high noise immunity. on chip memory includes 4k words of rom, and 192 bytes of static ram. 2. features the followings are some of the features on the hardware and software: fully cmos static design 8-bit data bus on chip eprom size: 4.0 k words internal ram size: 192 bytes 37 single word instructions 14-bit instructions 8-level stacks operating voltage: 2.5 v ~ 5.5 v (prd disable) 4.5 v ~ 5.5 v (prd enable) operating frequency: dc ~ 20 mhz the most fast execution time is 200 ns under 20 mhz in all single cycle in structions except the branch instruction addressing modes include direct, indirect and relative addressing modes power-on reset power edge-detector reset power range-detector reset sleep mode for power saving capture, compare, pwm module synchronous serial port with scm,i2c 12 interrupt sources: -external int pin -tmr0 timer, tmr1 timer, tmr2 timer -a/d conversion completion -port b<7:4> interrupt on change -ccp1, ccp2, scm, usar, usat, pcm a/d converter module: -8 analog inputs multiplexed into one a/d converter -8-bit resolution tmr0: 8-bit timer/counter tmr1: 16-bit timer/counter tmr2: 8-bit timer 4 types of oscillator can be selected by programming option: rc low cost rc oscillator lfxt low frequency crystal oscillator xtal standard crystal oscillator hfxt high frequency crystal oscillator on-chip rc oscillator based watchdog timer (wdt) 33 i/o pins with their own independent direction control 3. applications the application areas of this mdt10p74 range from appliance motor control and high speed auto-motive to low power remote transmitters/receivers, pointing devices, and telecommunications processors, such as remote controller, small in struments, chargers, toy, automobile and pc peripheral ? etc.
mdt10p74(ba) this specification are subject to be change d without notice. any latest information please preview http;//www.mdtic.com.tw p. 2 2008/6 ver. 1.6 4. pin assignment mdt10p74p11(dip) mdt10p74q11(qfp) mdt10p74l11 (plcc)
mdt10p74(ba) this specification are subject to be change d without notice. any latest information please preview http;//www.mdtic.com.tw p. 3 2008/6 ver. 1.6 5. order information device rom (words) ram (bytes) i/o a/d (8 bits) timer (8/16) ccp scm/ usart package mdt10p74p11 4k 192 33 8-channel 2/1 2 yes/yes dip mdt10p74q11 4k 192 33 8-channel 2/1 2 yes/yes qfp mdt10p74l11 4k 192 33 8-channel 2/1 2 yes/yes plcc 6. pin function description pin name i/o function description pa0~pa3, pa5 i/o port a, ttl input level / analog input channel pa4 i/o pa4, schmitt trigger input levels, open drain output pb0~pb7 i/o port b, ttl input level / pb0: external interrupt input pb4~pb7:interrupt on pin change pc0~pc7 i/o port c, schmitt trigger input levels pd0~pd7 i/o port d, schmitt trigger input levels / ttl input level pe0~pe2 i/o port e, schmitt trigger input levels / ttl input level analog input channel /mclr i master clear, schmitt trigger input levels osc1/clkin i oscillator input/external clock input osc2/clkout o oscillator output/in rc mode, the clkout pin has 1/4 frequency of clkin vdd power supply vss ground 7. memory map (a) register map address description bank0 00 indirect addressing register 01 rtcc 02 pcl 03 status 04 msr 05 port a 06 port b 07 port c 08 port d 09 port e
mdt10p74(ba) this specification are subject to be change d without notice. any latest information please preview http;//www.mdtic.com.tw p. 4 2008/6 ver. 1.6 address description 0a pchlat 0b ints 0c pifb1 0d pifb2 0e tmr1l 0f tmr1h 10 t1sta 11 tmr2 12 t2sta 13 scmbuf 14 scmctl 15 ccp1l 16 ccp1h 17 ccp1ctl 18 rcsc 19 txreg 1a rcreg 1b ccp2l 1c ccp2h 1d ccp2ctl 1e adres 1f ads0 20~7f general purpose register bank1 01 tmr 05 cpio a 06 cpio b 07 cpio c 08 cpio d 09 cpio e 0c pieb1 0d pieb2 0e psta 12 t2per 14 scmsta 18 txsc
mdt10p74(ba) this specification are subject to be change d without notice. any latest information please preview http;//www.mdtic.com.tw p. 5 2008/6 ver. 1.6 address description 19 brreg 1f ads1 a0~ff general purpose register (1) iar (indirect addr ess register): r00 (2) rtcc (real time counter/counter register): r01 (3) pc (program counter): r02, r0a write pc --- from pchlat write pc --- from pchlat ljump, lcall --- from instruction word rtwi, ret --- from stack a11 a10~a8 a7~a0 write pc --- from alu ljump, lcall --- from instruction word rtwi, ret, rtfi --- from stack (4) status (status register): r03 bit symbol function 0 c carry bit 1 hc half carry bit 2 z zero bit 3 /pf power down bit 4 /tf wdt timer overflow bit 5 rbs0 register bank select bit 0: 00h~7fh (bank0) 1: 80h~ffh (bank1) 7~6 -- general purpose bit
mdt10p74(ba) this specification are subject to be change d without notice. any latest information please preview http;//www.mdtic.com.tw p. 6 2008/6 ver. 1.6 (5) msr (memory bank select register): r04 memory bank select register 0: 00h~7fh (bank0) 1: 80h~ffh (bank1) b7 b6 b5 b4 b3 b2 b1 b0 indirect addressing mode (6) port a: r05 pa5~pa0, i/o register (7) port b: r06 pb7~pb0, i/o register (8) port c: r07 pc7~pc0, i/o register (9) port d: r08 pd7~pd0, i/o register (10) port e: r09 pe2~pe0, i/o register (11) pchlat: r0a (12) ints (interrupt status register): r0b bit symbol function 0 rbif port b change interrupt flag, set when pb <7 4> inputs change 1 intf set when int interrupt occurs 2 tif set when tmr0 overflows 3 rbie 0: disable pb change interrupt 1: enable pb change interrupt 4 ints 0: disable int interrupt 1: enable int interrupt 5 tis 0: disable tmr0 interrupt 1: enable tmr0 interrupt 6 peie 0: disable all peripheral interrupt 1: enable all peripheral interrupt 7 gis 0: disable global interrupt 1: enable global interrupt
mdt10p74(ba) this specification are subject to be change d without notice. any latest information please preview http;//www.mdtic.com.tw p. 7 2008/6 ver. 1.6 (13) pifb1 (peripheral interrupt flag bit): r0c bit symbol function 0 tmr1if tmr1 interrupt flag 0: tmr1 did not overflow 1: tmr1 overflowed 1 tmr2if tmr2 interrupt flag 0: no tmr2 to t2per match occurred 1: tmr2 to t2per match occurred 2 ccp1if ccp1 interrupt flag 0: no tmr1 capture/compare occurred 1: a tmr1 capture/compare occurred 3 scmif scm interrupt flag 0: waiting scm transmit/receive 1: the scm transmission/reception is complete 4 txif usart transmit interrupt flag 0: the usart transmit buffer is full 1: the usart transmit buffer is empty 5 rcif uasrt receive interrupt flag 0: the usart receive buffer is empty 1: the usart receive buffer is full 6 adif a/d interrupt flag 0: a/d conversion is not complete 1: a/d conversion completed 7 pcmif pcm read/write interrupt flag 0: no read or write has occurred 1: a read or a write has occurred (14) pifb2 (peripheral interrupt flag bit): r0d bit symbol function 0 ccp2if ccp2 interrupt flag 0: no tmr1 capture/compare occurred 1: a tmr1 capture/compare occurred 7~1 -- unimplemented (15) tmr1l: r0e the lsb of the 16-bit tmr1
mdt10p74(ba) this specification are subject to be change d without notice. any latest information please preview http;//www.mdtic.com.tw p. 8 2008/6 ver. 1.6 (16) tmr1h: r0f the msb of the 16-bit tmr1 (17) t1sta: r10 bit symbol function 0 tmr1on 0: stop tmr1 1: enable tmr1 1 tmr1clk 0: internal clock (fosc/4) 1: external clock from pin pc0 2 /t1sync tmr1clk = 1 0: synchronize external clock 1: do not synchronize external clock tmr1clk = 0 this bit is ignored 3 t1oscen 0: tmr1 oscillator is shut off 1: tmr1 oscillator is enable 5~4 t1ckps1 ~ t1ckps0 1 1 = 1:8 prescale value 1 0 = 1:4 prescale value 0 1 = 1:2 prescale value 0 0 = 1:1 prescale value 7~6 -- unimplemented (18) tmr2: r11 tmr2 register (19) t2sta: r12 bit symbol function 1~0 t2ckps1 ~ t2ckps0 0 0 = prescaler is 1 0 1 = prescaler is 4 1 x = prescaler is 16 2 tmr2on 0: tmr2 is off 1: tmr2 is on 7~3 -- unimplemented (20) scmbuf: r13 serial communication port buffer
mdt10p74(ba) this specification are subject to be change d without notice. any latest information please preview http;//www.mdtic.com.tw p. 9 2008/6 ver. 1.6 (21) scmctl: r14 bit symbol function 3~0 scm3 ~ scm0 0 0 0 0: scm master mode, clock = fosc/4 0 0 0 1: scm master mode, clock = fosc/16 0 0 1 0: scm master mode, clock = fosc/64 0 0 1 1: scm master mode, clock = tmr2 output/2 0 1 0 0: scm slave mode, clock = sck pin, /ss control enable 0 1 0 1: scm slave mode, clock = sck pin, /ss control disable 0 1 1 0: i2c slave mode, 7 bit address. 0 1 1 1: i2c slave mode, 10 bit address. 1 0 1 1: i2c firmware controlled master mode. 1 1 1 0: i2c slave mode, 7 bit addre ss with start and stop bit interrupts enabled. 1 1 1 1: i2c slave mode, 10 bit addre ss. with start and stop bit interrupts enabled. 4 cks 0: transmit happens on rising edge, receive on falling edge, idle state for clock is low level. 1: transmit happens on falling edge, receive on rising edge, idle state for clock is high level 5 scmen 0: disable scm, then pc3, pc4, pc5 is i/o port 1: enable scm 6 scmroi 0: no overflow 1: overflow 7 wcol 0: no collision 1: the scmbuf is written while it is still transmitting the previous word (22) ccp1l: r15 capture/compare/pwm lsb (23) ccp1h: r16 capture/compare/pwm msb
mdt10p74(ba) this specification are subject to be change d without notice. any latest information please preview http;//www.mdtic.com.tw p. 10 2008/6 ver. 1.6 (24) ccp1ctl: r17 bit symbol function 3~0 ccp1m3 ~ ccp1m0 0 0 0 0: ccp1 off 0 1 0 0: capture1 mode, every falling edge 0 1 0 1: capture1 mode, every rising edge 0 1 1 0: capture1 mode, every 4 th rising edge 0 1 1 1: capture1 mode, every 16 th rising edge 1 0 0 0: compare1 mode, set output on match 1 0 0 1: compare1 mode, clear output on match 1 0 1 0: compare1 mode, generate software interrupt on match 1 0 1 1: compare1 mode, trigger special event 1 1 x x: pwm1 mode 5~4 pwm1lsb these bits are the tw o lsbs of the pwm1 duty cycle 7~6 -- unimplemented (25) rcsc: r18 bit symbol function 0 rx9df 9 th bit of received data 1 oerf 0: no overrun error 1: overrun error 2 ferf 0: no framing error 1: framing error 3 -- unimplemented 4 crenf 0: disable continuous receive 1: enable continuous receive 5 srenf 0: disable single receive 1: enable single receive 6 rx9enf 0: select 8-bit reception 1: select 9-bit reception 7 spenf 0: serial port disable 1: serial port enable (26) txreg: r19 usart transmit register
mdt10p74(ba) this specification are subject to be change d without notice. any latest information please preview http;//www.mdtic.com.tw p. 11 2008/6 ver. 1.6 (27) rcreg: r1a usart receive register (28) ccp2l: r1b capture/compare/pwm lsb (29) ccp2h: r1c capture/compare/pwm msb (30) ccp2ctl: r1d bit symbol function 3~0 ccp2m3 ~ ccp2m0 0 0 0 0: ccp2 off 0 1 0 0: capture2 mode, every falling edge 0 1 0 1: capture2 mode, every rising edge 0 1 1 0: capture2 mode, every 4 th rising edge 0 1 1 1: capture2 mode, every 16 th rising edge 1 0 0 0: compare2 mode, set output on match 1 0 0 1: compare2 mode, clear output on match 1 0 1 0: compare2 mode, generate software interrupt on match 1 0 1 1: compare2 mode, trigger special event 1 1 x x: pwm2 mode 5~4 pwm2lsb these bits are the tw o lsbs of the pwm2 duty cycle 7~6 -- unimplemented (31) adres: r1e a/d result register high byte. the adr es register is not a writable register. (32) ads0: r1f bit symbol function 0 adrun 0: a/d converter module is shut off and consumes no operating current 1: a/d converter module is operating 1 -- unimplemented 2 go/doneb 0: a/d conversion not in progress 1: a/d conversion in progress 5~3 chs2~0 000: aic0 001: aic1 010: aic2 011: aic3 100: aic4 101: aic5 110: aic6 111: aic7
mdt10p74(ba) this specification are subject to be change d without notice. any latest information please preview http;//www.mdtic.com.tw p. 12 2008/6 ver. 1.6 bit symbol function 7~6 ascs1-0 00: fosc/2 01: fosc/8 10: fosc/32 11: f rc (*note) *note: determined by osc mode, hf: fosc/ 32, xt: fosc/8, rc: fosc/2, lf: fosc/2 (33) tmr (time mode register): r81 bit symbol function prescaler value rtcc rate wdt rate 2~0 ps2~0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 3 psc prescaler assignment bit 0: rtcc 1: watchdog timer 4 tce rtcc signal edge 0: increment on low-to-high transition on rtcc pin 1: increment on high-to-low transition on rtcc pin 5 tcs rtcc signal set 0: internal instruction cycle clock 1: transition on rtcc pin 6 ies interrupt edge select 0: interrupt on falling edge on pb0 1: interrupt on rising edge on pb0 7 pbph portb7~0 pull-hi 0: portb7~0 pull-hi are enable 1: portb7~0 pull-hi are disable (34) cpio a (control port i/o mode register): r85 ?0?, i/o pin in output mode ?1?, i/o pin in input mode (35) cpio b (control port i/o mode register): r86 ?0?, i/o pin in output mode ?1?, i/o pin in input mode (36) cpio c (control port i/o mode register): r87 ?0?, i/o pin in output mode ?1?, i/o pin in input mode (37) cpio d (control port i/o mode register): r88 ?0?, i/o pin in output mode ?1?, i/o pin in input mode
mdt10p74(ba) this specification are subject to be change d without notice. any latest information please preview http;//www.mdtic.com.tw p. 13 2008/6 ver. 1.6 (38) cpio e (control port i/o mode register): r89 bit symbol function 2~0 bit 2 ~ bit 0 port e control port i/o mode bits 0: i/o pin in output mode 1: i/o pin in input mode 3 -- unimplemented 4 pcmmode pcm mode select bit 0: general i/o mode 1: pcm mode 5 ibov input buffer overflow detect bit 0: no overflow occurred 1: overflow 6 obf output buffer full status bit 0: the output buffer has been read 1: the output buffer has not been read 7 ibf input buffer full status bit 0: no word has been received 1: a word has been received (39) pieb1: r8c bit symbol function 0 tmr1ie tmr1 interrupt enable bit 0: disable tmr1 interrupt 1: enable tmr1 interrupt 1 tmr2ie tmr2 interrupt enable bit 0: disable tmr2 interrupt 1: enable tmr2 interrupt 2 ccp1ie ccp1 interrupt enable bit 0: disable ccp1 interrupt 1: enable ccp1 interrupt 3 scmie scm interrupt enable bit 0: disable scm interrupt 1: enable scm interrupt 4 txie usart transmit interrupt enable bit 0: disable the usart transmit interrupt 1: enable the usart transmit interrupt
mdt10p74(ba) this specification are subject to be change d without notice. any latest information please preview http;//www.mdtic.com.tw p. 14 2008/6 ver. 1.6 bit symbol function 5 rcie usart receive interrupt enable bit 0: disable the usart receive interrupt 1: enable the usart receive interrupt 6 adie a/d interrupt enable bit 0: disable a/d interrupt 1: enable a/d interrupt 7 pcmie pcm r/w interrupt enable bit 0: disable the pcm interrupt 1: enable the pcm interrupt (40) pieb2: r8d bit symbol function 0 ccp2ie 0: d isable ccp2 interrupt 1 : enable ccp2 interrupt 7~1 -- unimplemented (41) psta: r8e bit symbol function 0 prdb 0: power range-detector reset occurred 1: no power range-detector reset occurred 1 porb 0: power on reset occurred 1: no power on reset occurred 7~2 -- unimplemented (42) t2per: r92 timer2 period (43) scmsta: r94 bit symbol function 0 bf 0: receive not complete 1: receive complete 1 i2c_ua (10 bit i2c mode) 0:address does not need to be updated. 1:indicates that the user needs to update the address in the sspadd register. 2 i2c_rwb 0:write 1:read 3 i2c_start 0:start bit was not detected last. 1:indicates that a start bit has been detected last.
mdt10p74(ba) this specification are subject to be change d without notice. any latest information please preview http;//www.mdtic.com.tw p. 15 2008/6 ver. 1.6 bit symbol function 4 i2c_stop 0:stop bit was not detected last. 1:indicates that a stop bit has been detected last. 5 i2c_dab 0:indicates that the last byte received or transmitted was address. 1:indicates that the last byte received or transmitted was data. 7~6 -- unimplemented (44) txsc: r98 bit symbol function 0 tx9df 9 th bit of transmit data 1 tsrcf 0: tsr full 1: tsr empty 2 hbrcf 0: low speed 1: high speed 3 -- unimplemented 4 umsf 0: usart asynchronous mode 1: usart synchronous mode 5 txenf 0: transmit disable 1: transmit enable 6 tx9enf 0: select 8-bit reception 1: select 9-bit reception 7 cssf 0: slave mode 1: master mode (45) brreg: r99 baud rate register (46) ads1 (a/d status register): r9f bit symbol function 2~0 pavm2~0 0 0 0: pa0~3, pa5, pe0~2 = analog input, vref = vdd 0 0 1: pa0~2, pa5, pe0~2 = analog input, vref = pa3 0 1 0: pa0~3, pa5 = analog input, pe0~2 = digital i/o, vref = vdd 0 1 1: pa0~2, pa5 = analog input, pe0~2 = digital i/o, vref = pa3 1 0 0: pa0, 1, 3 = analog input, pa2, 5, pe0~2 = digital i/o, vref = vdd 1 0 1: pa0, 1 = analog input, pa2, 5, pe0~2 = digital i/o, vref = pa3 1 1 x: pa0~3, 5, pe0~2 = digital i/o 7~3 -- unimplemented
mdt10p74(ba) this specification are subject to be change d without notice. any latest information please preview http;//www.mdtic.com.tw p. 16 2008/6 ver. 1.6 (47) configurable options for eprom (set by writer) oscillator type rc oscillator hfxt oscillator xtal oscillator lfxt oscillator watchdog timer control watchdog timer disable all the time watchdog timer enable all the time power-range control power-range disable power-range enable oscillator-start timer control 0ms 75ms power-edge detect security state ped disable security disable ped enable security enable (b) program memory address description 000-fff program memory 000 the starting address of power on, exte rnal reset or wdt time-out reset. 004 interrupt vector
mdt10p74(ba) this specification are subject to be change d without notice. any latest information please preview http;//www.mdtic.com.tw p. 17 2008/6 ver. 1.6 8. reset condition for all registers register address power-on reset, power range detector reset /mclr or wdt reset wake-up from sleep iar 00h n/a n/a n/a rtcc 01h xxxx xxxx uuuu uuuu uuuu uuuu pc 0ah,02h 0000 0000 0000 0000 0000 0000 pc+1 status 03h 0001 1xxx 000# #uuu 000# #uuu msr 04h xxxx xxxx uuuu uuuu uuuu uuuu port a 05h --xx xxxx --uu uuuu --uu uuuu port b 06h xxxx xxxx uuuu uuuu uuuu uuuu port c 07h xxxx xxxx uuuu uuuu uuuu uuuu port d 08h xxxx xxxx uuuu uuuu uuuu uuuu port e 09h ---- -xxx ---- -uuu ---- -uuu pchlat 0ah ---0 0000 ---0 0000 ---u uuuu ints obh 0000 000x 0000 000u uuuu uuuu pifb1 0ch 0000 0000 0000 0000 uuuu uuuu pifb2 0dh ---- ---0 ---- ---0 ---- ---u tmr1l 0eh xxxx xxxx uuuu uuuu uuuu uuuu tmr1h 0fh xxxx xxxx uuuu uuuu uuuu uuuu t1sta 10h --00 0000 --uu uuuu --uu uuuu tmr2 11h 0000 0000 0000 0000 uuuu uuuu t2sta 12h ---- -000 ---- -uuu ---- -uuu scmbuf 13h xxxx xxxx uuuu uuuu uuuu uuuu scmctl 14h 0000 0000 0000 0000 uuuu uuuu ccp1l 15h xxxx xxxx uuuu uuuu uuuu uuuu ccp1h 16h xxxx xxxx uuuu uuuu uuuu uuuu ccp1ctl 17h --00 0000 --00 0000 --uu uuuu rcsc 18h 0000 -00x 0000 -00x uuuu -uuu txreg 19h 0000 0000 0000 0000 uuuu uuuu rcreg 1ah 0000 0000 0000 0000 uuuu uuuu ccp2l 1bh xxxx xxxx uuuu uuuu uuuu uuuu ccp2h 1ch xxxx xxxx uuuu uuuu uuuu uuuu
mdt10p74(ba) this specification are subject to be change d without notice. any latest information please preview http;//www.mdtic.com.tw p. 18 2008/6 ver. 1.6 register address power-on reset, power range detector reset /mclr or wdt reset wake-up from sleep ccp2ctl 1dh --00 0000 --00 0000 --uu uuuu adres 1eh xxxx xxxx uuuu uuuu uuuu uuuu ads0 1fh 0000 00-0 0000 00-0 uuuu uu-u tmr 81h 1111 1111 1111 1111 uuuu uuuu cpioa 85h --11 1111 --11 1111 --uu uuuu cpiob 86h 1111 1111 1111 1111 uuuu uuuu cpioc 87h 1111 1111 1111 1111 uuuu uuuu cpiod 88h 1111 1111 1111 1111 uuuu uuuu cpioe 89h 0000 -111 0000 -111 uuuu -uuu pieb1 8ch 0000 0000 0000 0000 uuuu uuuu pieb2 8dh ---- ---0 ---- ---0 ---- ---u psta 8eh ---- --0u ---- --uu ---- --uu t2per 92h 1111 1111 1111 1111 1111 1111 scmsta 94h ---- ---0 ---- ---0 ---- ---u txsc 98h 0000 -010 0000 -010 uuuu -uuu brreg 99h 0000 0000 0000 0000 uuuu uuuu ads1 9fh ---- -000 ---- -000 ---- -uuu note : u unchanged, x unknown, - unimplemented, read as ?0? # value depends on the condition of the following table condition status: bit 4 status: bit 3 psta: bit 1 psta: bit 0 /mclr reset (not during sleep) u u u u /mclr reset during sleep 1 0 u u wdt reset (not during sleep) 0 1 u u wdt reset during sleep 0 0 u u power-on reset 1 1 0 x power-range reset 1 1 u 0 note : u unchanged, x unknown, - unimplemented, read as ?0?
mdt10p74(ba) this specification are subject to be change d without notice. any latest information please preview http;//www.mdtic.com.tw p. 19 2008/6 ver. 1.6 9. instruction set instruction code mnemonic operands function operating status 010000 00000000 nop no operation none 010000 00000001 clrwt clear watchdog timer 0 wt tf, pf 010000 00000010 sleep sleep mode 0 wt, stop osc tf, pf 010000 00000011 tmode load w to tmode register w tmode none 010000 00000100 ret return from subroutine stack pc none 010000 00000rrr cpio r control i/o port register w cpio r none 010001 1rrrrrrr stwr r store w to register w r none 011000 trrrrrrr ldr r, t load register r t z 111010 iiiiiiii ldwi i load immediate to w i w none 010111 trrrrrrr swapr r, t swap halves register [r(0~3) ? r(4~7)] t none 011001 trrrrrrr incr r, t increment register r + 1 t z 011010 trrrrrrr incrsz r, t increment register, skip if zero r + 1 t none 011011 trrrrrrr addwr r, t add w and register w + r t c, hc, z 011100 trrrrrrr subwr r, t subtract w from register r w t or (r+/w+1 t) c, hc, z 011101 trrrrrrr decr r, t decrement register r 1 t z 011110 trrrrrrr decrsz r, t decrement register, skip if zero r 1 t none 010010 trrrrrrr andwr r, t and w and register r w t z 110100 iiiiiiii andwi i and w and immediate i w w z 010011 trrrrrrr iorwr r, t inclu. or w and register r w t z 110101 iiiiiiii iorwi i inclu. or w and immediate i w w z 010100 trrrrrrr xorwr r, t exclu. or w and register r ? w t z 110110 iiiiiiii xorwi i exclu. or w and immediate i ? w w z 011111 trrrrrrr comr r, t complement register /r t z 010110 trrrrrrr rrr r, t rotate right register r(n) r(n-1), c r(7), r(0) c c 010101 trrrrrrr rlr r, t rotate left register r(n) r(n+1), c r(0), r(7) c c 010000 1xxxxxxx clrw clear working register 0 w z 010001 0rrrrrrr clrr r clear register 0 r z 0000bb brrrrrrr bcr r, b bit clear 0 r(b) none 0010bb brrrrrrr bsr r, b bit set 1 r(b) none 0001bb brrrrrrr btsc r, b bit test, skip if clear skip if r(b)=0 none 0011bb brrrrrrr btss r, b bit test, skip if set skip if r(b)=1 none 100nnn nnnnnnnn lcall n long call subroutine n pc, pc+1 stack none
mdt10p74(ba) this specification are subject to be change d without notice. any latest information please preview http;//www.mdtic.com.tw p. 20 2008/6 ver. 1.6 instruction code mnemonic operands function operating status 101nnn nnnnnnnn ljump n long jump to address n pc none 110111 iiiiiiii addwi i add immediate to w w+i w c,hc,z 110001 iiiiiiii rtwi i return, place immediate to w stack pc,i w none 111000 iiiiiiii subwi i subtract w from immediate i-w w c,hc,z 010000 00001001 rtfi reture from interrupt stack pc,1 gis none note : w : working register b : bit position wt : watchdog timer t : target tmode : tmode mode register 0 : working register cpio : control i/o port register 1 : general register tf : timer overflow flag r : general register address pf : power loss flag c : carry flag pc : program counter hc : half carry osc : oscillator z : zero flag inclu. : inclusive ? ? / : complement exclu. : exclusive ? ? ? x : don?t care and : logic and ? ? i : immediate data ( 8 bits ) n : immediate address 10. electrical characteristics *note: temperature=25c 1. operation current: (1) hf (c=10p), wdt ? disable, prd ? disable 4m 10m 20m sleep 2.5v 480ua 1ma 2.1ma 1ua 3.0v 600ua 1.3ma 2.5ma 1ua 4.0v 1ma 2ma 4ma 1ua 5.0v 1.5ma 2.9ma 5.3ma 1ua 5.5v 1.8ma 4ma 6.8ma 1ua these parameters are for reference only. (2) xt (c=10p), wdt ? disable, prd ? disable 1m 4m 10m sleep 2.5v 130ua 440ua 1ma 1ua 3.0v 160ua 560ua 1.2ma 1ua 4.0v 400ua 900ua 2ma 1ua 5.0v 700ua 1.3ma 2.8ma 1ua 5.5v 940ua 1.6ma 3.3ma 1ua these parameters are for reference only.
mdt10p74(ba) this specification are subject to be change d without notice. any latest information please preview http;//www.mdtic.com.tw p. 21 2008/6 ver. 1.6 (3) lf (c=10p), wdt ? disable, prd ? disable 32k 455k 1m sleep 2.5v 30ua 80ua 170ua 1ua 3.0v 40ua 120ua 210ua 1ua 4.0v 90ua 210ua 420ua 1ua 5.0v 180ua 450ua 600ua 1ua 5.5v 270ua 600ua 900ua 1ua these parameters are for reference only. (4) rc, wdt ? disable, p rd ? disable, @vdd = 5.0v c r freq. current 4.7k 11.8m 4ma 10k 5.8m 2ma 47k 1.35m 600ua 100k 644k 400ua 300k 196k 250ua 3p 470k 136k 200ua 4.7k 6m 2.7ma 10k 3.04m 1.5ma 47k 692k 500ua 100k 327k 350ua 300k 98k 250ua 20p 470k 70k 200ua 4.7k 2.18m 1.7ma 10k 1.09m 900ua 47k 240k 300ua 100k 112k 250ua 300k 34k 200ua 100p 470k 25k 200ua 4.7k 963k 1.4ma 10k 464k 700ua 47k 101k 250ua 100k 47k 200ua 300k 14k 200ua 300p 470k 10k 200ua these parameters are for reference only.
mdt10p74(ba) this specification are subject to be change d without notice. any latest information please preview http;//www.mdtic.com.tw p. 22 2008/6 ver. 1.6 (5) rc, wdt ? disable, p rd ? disable, @vdd = 3.0v c r freq. current 4.7k 11.6m 2ma 10k 6.52m 1.2ma 47k 1.62m 300ua 100k 784k 160ua 300k 242k 60ua 3p 470k 173k 60ua 4.7k 6.88m 1.5ma 10k 3.65m 800ua 47k 868k 170ua 100k 415k 100ua 300k 127k 60ua 20p 470k 91k 60ua 4.7k 2.94m 1ma 10k 1.52m 500ua 47k 348k 120ua 100k 116k 60ua 300k 50k 60ua 100p 470k 36k 60ua 4.7k 1.42m 800ua 10k 724k 400ua 47k 164k 100ua 100k 79k 60ua 300k 24k 60ua 300p 470k 17k 60ua these parameters are for reference only. 2. input voltage (vdd = 5v): pa~pc min max ttl vss 0.8v vil schmitt trigger vss 0.6v ttl 3.0v vdd vih schmitt trigger 3.8v vdd these parameters are for reference only.
mdt10p74(ba) this specification are subject to be change d without notice. any latest information please preview http;//www.mdtic.com.tw p. 23 2008/6 ver. 1.6 input voltage (vdd = 3v): pa~pc min max ttl vss 0.4v vil schmitt trigger vss 0.2v ttl 2.0v vdd vih schmitt trigger 2.6v vdd these parameters are for reference only. 3. output voltage (vdd = 5v): pa~pc condition voh 3.3v ioh = -20ma vol 0.9v iol = 20ma voh 4.2v ioh = -5ma vol 0.6v iol = 5ma these parameters are for reference only. output voltage (vdd = 3v): pa~pc condition voh 1.6v ioh = -10ma vol 0.6v iol = 10ma voh 2.4v ioh = -5ma vol 0.5v iol = 5ma these parameters are for reference only. 4. output current (max.) (vdd = 5v): current source current 25ma sink current 40ma these parameters are for reference only. 5. the basic wdt time-out cycle time: time 2.5v 25ms 3.0v 23ms 4.0v 20ms 5.0v 18ms 5.5v 17ms
mdt10p74(ba) this specification are subject to be change d without notice. any latest information please preview http;//www.mdtic.com.tw p. 24 2008/6 ver. 1.6 these parameters are for reference only. 6. prd: (1) prd reset voltage: voltage vih 4.2v 10% vil 3.8v 10% these parameters are for reference only. (2) prd reset current: current 5.0v 120ua 4.0v 100ua these parameters are for reference only. 7. pull high resistor: vdd 5v 3v pb7~0 50k 20% 100k 20% these parameters are for reference only. 8. mclr filter time: vdd 5v time 1000ns 20% these parameters are for reference only.

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